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S34ML08G2 8 gb, 4-bit ecc, x8 i/o and 3 v vcc nand flash memory for embedded cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-00484 rev. *i revised january 17, 2018 distinctive characteristics ? density C 8 gb (4 gb x 2) ? architecture (for each 4 gb device) C input / output bus width: 8-bits C page size: (2048 + 128) bytes; 128-byte spare area C block size: 64 pages or (128k + 8k) bytes C plane size C 2048 blocks per plane or (256m + 16m) bytes Cdevice size C 2 planes per device or 512 mbyte ? nand flash interface C open nand flash interface (onfi) 1.0 compliant C address, data and commands multiplexed ? supply voltage C 3.3v device: vcc = 2.7v ~ 3.6v ? security C one time programmable (otp) area C serial number (unique id) C hardware program/erase di sabled during power transition ? additional features C supports multiplane program and erase commands C supports copy back program C supports multiplane copy back program C supports read cache ? electronic signature C manufacturer id: 01h ? operating temperature C industrial: -40c to 85c C industrial plus: -40c to 105c performance ? page read / program C random access: 30 s (max) C sequential access: 25 ns (min) C program time / multiplane program time: 300 s (typ) ? block erase / multiplane erase C block erase time: 3.5 ms (typ) ? reliability C 100,000 program / erase cycles (typ) (with 4-bit ecc per 528 bytes) C 10 year data retention (typ) C blocks zero and one are valid a nd will be valid for at least 1 000 program-erase cycles with ecc ? package options C lead free and low halogen C 48-pin tsop 12 x 20 x 1.2 mm C 63-ball bga 11 x 9 x 1 mm
document number: 002-00484 rev. *i page 2 of 16 S34ML08G2 contents 1. general description ..................................................... 3 2. connection diagram .................................................... 3 3. pin description ............................................................. 4 4. block diagrams ............................................................ 5 5. addressing ............................................................... .... 6 6. read status enhanced ................................................ 6 7. read id ............................................................... ........... 7 7.1 read parameter page ......................................... .......... 8 8. electrical characteristics .......................................... 10 8.1 valid blocks ................................................ ................. 10 8.2 recommended operating conditions.......................... 1 0 8.3 dc characteristics .......................................... ............. 10 8.4 pin capacitance............................................. ............... 11 8.5 power consumptions and pin capacitance for allowed stacking configur ations ............................ . 11 9. physical interface ....................................................... 11 9.1 physical diagram ............................................ .............. 12 10. ordering information .................................................. 14 11. document history ....................................................... 15 sales, solutions, and legal information ....................... ... 16 worldwide sales and design supp ort ............ ........ .......1 6 products ...................................................... ..................16 psoc? solutions ............................................... ...........16 cypress developer community . .................................. ..16 technical support ........... .................................. ............16
document number: 002-00484 rev. *i page 3 of 16 S34ML08G2 1. general description the cypress ? S34ML08G2 8-gb nand is offered in 3.3 v cc with x8 i/o interface. this do cument contains information for the S34ML08G2 device, which is a dual -die stack of two s34ml04g2 di e. for detailed specif ications, please refe r to the discrete di e datasheet: s34ml01g2_04g2 . 2. connection diagram figure 1. 48-pin tsop1 contact x8 device (1 ce 8 gb) note 1. these pins should be c onnected to power supply or ground (as designated) following the onfi specification, however they might not be bonded internally. figure 2. 63-bga contact, x8 device, single ce (top view) nc nc nc nc nc nc r/b# re# ce# nc nc vcc vss nc nc cle ale we# wp# nc nc nc nc nc vss nc nc nc i/o7 i/o6 i/o5 i/o4 nc vcc nc vcc vss nc vcc nc i/o3 i/o2 i/o1 i/o0 nc nc nc vss 12 13 37 36 25 48 1 24 nand flash tsop1 (x8) (1) (1) (1) (1) f3 f4 f5 f6 f7 f8 e3 e4 e5 e6 e7 e8 d3 d4 d5 d6 d7 d8 c3 c4 c5 c6 c7 c8 rb# we# ce# vss ale wp# nc nc nc cle re# vcc nc nc nc nc nc nc g3 g4 g5 g6 g7 g8 nc vss nc nc nc nc h3 h4 h5 h6 h7 h8 v cc nc nc nc i/o0 nc b9 a9 nc nc a2 nc nc nc nc nc vcc nc b10 a10 nc nc b1 a1 nc nc j3 j4 j5 j6 j7 j8 i/o7 i/o5 v cc nc i/o1 nc k3 k4 k5 k6 k7 k8 v ss i/o6 i/o4 i/o3 i/o2 v ss l9 nc l2 nc l10 nc l1 nc m9 nc m2 nc m10 nc m1 nc
document number: 002-00484 rev. *i page 4 of 16 S34ML08G2 3. pin description notes 1. a 0.1 f capacitor should be connected between the v cc supply voltage pin and the v ss ground pin to decouple the current su rges from the power supply. the pcb track widths must be sufficient to carry the curre nts required during program and erase operations. 2. an internal voltage detector di sables all functions whenever v cc is below 1.8v to protect the device from any involuntary program/erase during power transitions. table 1. pin description pin name description i/o0 - i/o7 inputs/outputs . the i/o pins are used for command input, address input, data input, and data output. the i/o pins float to high-z when the device is deselected or the outputs are disabled. cle command latch enable. this input activates the latching of the i/o inputs inside the command register on the rising edge of write enable (we#). ale address latch enable. this input activates the latchi ng of the i/o inputs inside the address register on the rising edge of write enable (we#). ce# chip enable. this input contro ls the selection of the device . when the device is not busy ce# low selects the memory. we# write enable. this input latches command, address and data. the i/o inputs are latched on the rising edge of we#. re# read enable. the re# input is the serial data-out control, and when active d rives the data onto the i/o bus. data is valid t rea after the falling edge of re# which als o increments the internal colu mn address counter by one. wp# write protect. the wp# pin, when low, provides hardware protection against und esired data modification (program / erase). r/b# ready busy . the ready/busy output is an open drain pin that signals the s tate of the memory. vcc supply voltage . the v cc supplies the power for all the op erations (read, program, eras e). an internal lock circuit prevents the insertion of commands when v cc is less than v lko . vss ground. nc not connected.
document number: 002-00484 rev. *i page 5 of 16 S34ML08G2 4. block diagrams figure 3. functional block diagram 8 gb figure 4. block diagr am 1 ce (4 gb x 8) address register/ counter controller command interface logic command register data register re# i/o buffer y decoder page buffer x d e c o d e r nand flash memory array wp# ce# we# cle ale i/o0~i/o7 program erase hv generation 8192 mbit + 512 mbit (8 gb device) io0~io7 ce# we# r/b# re# vss ale vcc cle wp# io0~io7 io0~io7 ce# ce# we# we# r/b# r/b# re# re# vss vss ale ale vcc vcc cle cle wp# wp# 4 gb x8 nand flash memory#1 4 gb x8 nand flash memory#2
document number: 002-00484 rev. *i page 6 of 16 S34ML08G2 5. addressing notes 1. cax = column address bit. 2. pax = page address bit. 3. pla0 = plane address bit zero. 4. bax = block address bit. 5. block address concatenated with page address and plane address = actual page address, also known as the row address. 6. a30 for 8 gb (4 gb x 2 ? ddp) (1ce). for the address bits, th e following rules apply: ? a0 - a11: column address in the page ? a12 - a17: page address in the block ? a18: plane address (for multipl ane operations) / block address (for normal operations) ? a19 - a30: block address 6. read status enhanced read status enhanced is used to retrieve the status value for a previous operation in the following cases: ? in the case of concurrent oper ations on a multi-die stack. when two dies are stacked to for m a dual-die package (ddp), it is possible to run one operation on the first die, then activat e a different operation on the seco nd die, for example: erase while read, read while program, etc. ? in the case of multiplane o perations in the same die. table 2. address cycle map bus cycle i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 1st / col. add. 1 a0 (ca0) a1 (ca1) a2 (ca2) a3 (ca3) a4 (ca4) a5 (ca 5) a6 (ca6) a7 (ca7) 2nd / col. add. 2 a8 (ca8) a9 (ca9) a10 (ca10) a11 (ca11) low low low l ow 3rd / row add. 1 a12 (pa0) a13 (pa1) a14 (pa2) a15 (pa3) a16 (pa4) a1 7 (pa5) a18 (pla0) a19 (ba0) 4th / row add. 2 a20 (ba1) a21 (ba2) a22 (ba3) a23 (ba4) a24 (ba5) a2 5 (ba6) a26 (ba7) a27 (ba8) 5th / row add. 3 (6) a28 (ba9) a29 (ba10) a30 (ba11) low low low low low
document number: 002-00484 rev. *i page 7 of 16 S34ML08G2 7. read id the device contains a product id entification mode , initiated by writing 90h to the command reg ister, followed by an address in put of 00h. note : if you want to execute read st atus command (0x70) after read id sequence, you should input dummy command (0x00) before read status command (0x70). for the S34ML08G2 device, five read cycles sequentially output the manufacturer code (01h), and the device code and 3rd, 4th, and 5th cycle id, respectively. the command register remains in rea d id mode until further co mmands are issued to it. figure 5. read id operation timing 8 gb 5 th id data table 3. read id for supported configurations density org v cc 1st 2nd 3rd 4th 5th 4 gb x8 3.3v 01h dch 90h 95h 56h 8 gb (4 gb x 2 C ddp with one ce#) x8 3.3v 01h d3h d1h 95h 5ah table 4. read id byte 5 description description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 ecc level 1 bit / 512 bytes 2 bit / 512 bytes 4 bit / 512 bytes 8 bit / 512 bytes 0 0 0 1 1 0 1 1 plane number 1 2 4 8 0 0 0 1 1 0 1 1 plane size (without spare area) 64 mb 128 mb 256 mb 512 mb 1 gb 2 gb 4 gb 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 reserved 0 ce# we# cle re# ale twhr tar trea read id command address 1 cycle maker code device code 3rd cycle 4th cycle 5th cycle i/ox 01h 90h 00h 95h d3h 5ah d1h
document number: 002-00484 rev. *i page 8 of 16 S34ML08G2 7.1 read parameter page the device supports the onfi rea d parameter page operation, ini tiated by writing ech to the com mand register, followed by an address input of 00h. the comma nd register remains in parameter page mode until further co mmands are issued to it. table 5 explains the parameter fields. note: for 32nm cypress nand, for a particular condition, the read pa rameter page command does not give the correct values. to overcome this issue, the host mus t issue a reset command before the read parameter page comma nd. issuance of reset before the read parameter p age command will provide the correct values and will not out put 00h values. table 5. parameter page description byte o/m description values revision information and features block 0-3 m parameter page signature byte 0: 4fh, o byte 1: 4eh, n byte 2: 46h, f byte 3: 49h, i 4fh, 4eh, 46h, 49h 4-5 m revision number 2-15 reserved (0) 1 1 = supports onfi version 1.0 0 reserved (0) 02h, 00h 6-7 m features supported 5-15 reserved (0) 4 1 = supports odd to even page copyback 3 1 = supports interleaved operations 2 1 = supports non-sequential page programming 1 1 = supports multiple lun operations 0 1 = supports 16-bit data bus width 1eh, 00h 8-9 m optional commands supported 6-15 reserved (0) 5 1 = supports read unique id 4 1 = supports copyback 3 1 = supports read status enhanced 2 1 = supports get feat ures and set features 1 1 = supports read cache commands 0 1 = supports page cache program command 3bh, 00h 10-31 reserved (0) 00h manufacturer information block 32-43 m device manufacturer (12 ascii characters) 53h, 50h, 41h, 4eh, 53h, 49h, 4fh, 4eh, 20h, 20h, 20h, 20h 44-63 m device model (20 ascii characters) 53h, 33h, 34h, 4dh, 4ch, 30h, 38h, 47h, 32h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h 64 m jedec manufacturer id 01h 65-66 o date code 00h 67-79 reserved (0) 00h memory organization block 80-83 m number of data bytes per page 00h, 08h, 00h, 00h 84-85 m number of spare bytes per page 80h, 00h 86-89 m number of data bytes per partial page 00h, 00h, 00h, 00 h 90-91 m number of spare bytes per partial page 00h, 00h 92-95 m number of pages per block 40h, 00h, 00h, 00h 96-99 m number of blocks per logi cal unit (lun) 00h, 10h, 00h, 00h 100 m number of logical units (luns) 02h 101 m number of address cycles 4-7 column address cycles 0-3 row address cycles 23h 102 m number of bits per cell 01h
document number: 002-00484 rev. *i page 9 of 16 S34ML08G2 note 1. ?o? stands for optional, ?m? for mandatory. 103-104 m bad blocks maximum per lun 50h, 00h 105-106 m block endurance 01h, 05h 107 m guaranteed valid blocks at beginning of target 01h 108-109 m block endurance for guaranteed valid blocks 01h, 03h 110 m number of programs per page 04h 111 m partial programming attributes 5-7 reserved 4 1 = partial page layout is partial page data followed by partial page spare 1-3 reserved 0 1 = partial page programming has constraints 00h 112 m number of bits ecc correctability 04h 113 m number of interleaved address bits 4-7 reserved (0) 0-3 number of interleaved address bits 01h 114 o interleaved operation attributes 4-7 reserved (0) 3 address restrictions for program cache 2 1 = program cache supported 1 1 = no block address restrictions 0 overlapped / concurrent interleaving support 04h 115-127 reserved (0) 00h electrical parameters block 128 m i/o pin capacitance 0ah 129-130 m timing mode support 6-15 reserved (0) 5 1 = supports timing mode 5 4 1 = supports timing mode 4 3 1 = supports timing mode 3 2 1 = supports timing mode 2 1 1 = supports timing mode 1 0 1 = supports timing mode 0, shall be 1 1fh, 00h 131-132 o program cache timing mode support 6-15 reserved (0) 5 1 = supports timing mode 5 4 1 = supports timing mode 4 3 1 = supports timing mode 3 2 1 = supports timing mode 2 1 1 = supports timing mode 1 0 1 = supports timing mode 0 1fh, 00h 133-134 m t prog maximum page program time (s) bch, 02h 135-136 m t bers maximum block erase time (s) 10h, 27h 137-138 m t r maximum page read time (s) 1eh, 00h 139-140 m t ccs minimum change column setup time (ns) c8h, 00h 141-163 reserved (0) 00h vendor block 164-165 m vendor specific revision number 00h 166-253 vendor specific 00h 254-255 m integrity crc 16h, 26h redundant parameter pages 256-511 m value of bytes 0-255 repeat value of bytes 0-255 512-767 m value of bytes 0-255 repeat value of bytes 0-255 768+ o additional redundant parameter pages ffh table 5. parameter page description (continued) byte o/m description values
document number: 002-00484 rev. *i page 10 of 16 S34ML08G2 8. electrical c haracteristics 8.1 valid blocks note 1. each 4 gb has maximum 80 bad blocks. 8.2 recommended operating conditions 8.3 dc characteristics notes 1. all v cc pins, and v ss pins respectively, are shorted together. 2. values listed in this table refer to the complete voltage range for v cc and to a single device in case of device stacking. 3. all current measurements are performed with a 0.1 f capacitor connected between the v cc supply voltage pin and the v ss ground pin. 4. standby current measurement can be performed after the devic e has completed the initialization process at power up. table 6. valid blocks device symbol min typ max unit s34ml04g2 n vb 4016 4096 blocks S34ML08G2 n vb 8032 (1) 8192 blocks table 7. recommended operating conditions parameter symbol min typ max units vcc supply voltage vcc 2.7 3.3 3.6 v ground supply voltage vss 0 0 0 v table 8. dc characteristics and operating conditions parameter symbol test conditions min typ max units power on current i cc0 ffh command input after power on 50 per device ma operating current sequential read i cc1 t rc = t rc (min) ce# = v il , iout = 0 ma 1530ma program i cc2 normal 15 30 ma cache 15 30 ma erase i cc3 15 30 ma standby current, (ttl) i cc4 ce# = v ih , wp# = 0v/vcc 1ma standby current, (cmos) i cc5 ce# = v cc -0.2, wp# = 0/v cc 1050a input leakage current i li v in = 0 to v cc (max) 10 a output leakage current i lo v out = 0 to v cc (max) 10 a input high voltage v ih v cc x 0.8 v cc + 0.3 v input low voltage v il -0.3v cc x 0.2 v output high voltage v oh i oh = -400 a 2.4 v output low voltage v ol i ol = 2.1 ma 0.4 v output low current (r/b#) i ol(r/b#) v ol = 0.4v 8 10 ma erase and program lockout voltage v lko 1.8v
document number: 002-00484 rev. *i page 11 of 16 S34ML08G2 8.4 pin capacitance note 1. for the stacked devices version the input is 10 pf x [number of stacked chips] and the input/output is 10 pf x [number of sta cked chips]. 8.5 power consumptions and pin ca pacitance for allowed stacking configurations when multiple dies are stacked in the same package, the power c onsumption of the sta ck will increase according to the number o f chips. as an example, the standby current is the sum of the sta ndby currents of all the chips, w hile the active power consumpt ion depends on the number of chips c oncurrently executing different operations. when multiple dies are stacked in the same package the pin/ball capacitance for the single inpu t and the single input/output o f the combo package must be calculated based on the number of chips s haring that input or that pin/ball. 9. physical interface table 9. pin capacitanc e (ta = 25c, f=1.0 mhz) parameter symbol test condition min max unit input c in v in = 0v 10 pf input / output c io v il = 0v 10 pf
document number: 002-00484 rev. *i page 12 of 16 S34ML08G2 9.1 physical diagram 9.1.1 48-pin thin small outline package (tsop1) figure 6. ts2 48 48- lead plastic thin sm all outline, 12 x 20 mm, package outline 5007 \ f16-038 \ 6.5.13 package ts2 48 jedec mo-142 (d) dd symbol min nom max a --- --- 1.20 a1 0.05 --- 0.15 a2 0.95 1.00 1.05 b1 0.17 0.20 0.23 b 0.17 0.22 0.27 c1 0.10 --- 0.16 c 0.10 --- 0.21 d 19.80 20.00 20.20 d1 18.30 18.40 18.50 e 11.90 12.00 12.10 e 0.50 basic l 0.50 0.60 0.70 o 0? --- 8 r 0.08 --- 0.20 n48 notes: 1. dimensions are in millimeters (mm). (dimensioning and tolerancing conform to ansi y14.5m-1994). 2. pin 1 identifier for standard pin out (die up). 3. pin 1 identifier for reverse pin out (die down): ink or laser mark. 4. to be determined at the seating plane -c- . the seating plane is defined as the plane of contact that is made when the package leads are allowed to rest freely on a flat horizontal surface. 5. dimensions d1 and e do not include mold protrusion. allowable mold protrusion on e is 0.15mm per side and on d1 is 0.25mm per side. 6. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm total in excess of b dimension at max. material condition. dambar cannot be located on lower radius or the foot. minimum space between protrusion and an adjacent lead to be 0.07mm. 7. these dimensions apply to the flat section of the lead between 0.10mm and 0.25mm from the lead tip. 8. lead coplanarity shall be within 0.10mm as measured from the seating plane. 9. dimension "e" is measured at the centerline of the leads.
document number: 002-00484 rev. *i page 13 of 16 S34ML08G2 9.1.2 63-pin ball grid array (bga) figure 7. vld063 63-pin bga, 11 mm x 9 mm package g5013 \ 16-038.28 \ 6.5.13 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jep95, section 3, spp-020. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the total number of populated solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0. when there is an even number of solder balls in the outer row, sd = ed/2 and se = ee/2. 8. "+" indicates the theoretical center of depopulated balls. 9 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. package vld 063 jedec m0-207(m) 11.00 mm x 9.00 mm package symbol min nom max note a --- --- 1.00 profile a1 0.25 --- --- ball height d 11.00 bsc. body size e 9.00 bsc. body size d1 8.80 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 12 matrix size d direction me 10 matrix size e direction n 63 ball count b 0.40 0.45 0.50 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc. ball pitch sd 0.40 bsc. solder ball placement se 0.40 bsc. solder ball placement a3-a8,b2-b8,c1,c2,c9,c10 depopulated solder balls d1,d2,d9,d10,e1,e2,e9,e10 f1,f2,f9,f10,g1,g2,g9,g10 h1,h2,h9,h10,j1,j2,j9,j10 k1,k2,k9,k10 l3-l8,m3-m8
document number: 002-00484 rev. *i page 14 of 16 S34ML08G2 10. ordering information the ordering part number is form ed by a valid combination of th e following: valid combinations valid combinations list configur ations planned to be supported in volume for th is device. consult your l ocal sales office to c onfirm availability of specific valid c ombinations and to check on new ly released combinations. s34ml 08g 2 01 t f i 00 0 packing type 0 = tray 3 = 13 tape and reel model number 00 = standard interface / onfi (x8) temperature range i = industrial (C40c to + 85c) a = industrial with aecq-100 and gt grade (-40?c to +85?c) v = industrial plus (-40c to +105c) b = industrial plus with aecq-100 and gt grade (-40?c to +105?c) materials set f = lead (pb)-free h = lead (pb)-free and low halogen package b = bga t = tsop bus width 00 = x8 nand, single die 04 = x16 nand, single die 01 = x8 nand, dual die 05 = x16 nand, dual die technology 2 = cypress nand revision 2 (32 nm) density 01g = 1 gb 02g = 2 gb 04g = 4 gb 08g = 8 gb device family s34ml cypress slc nand flash memory for embedded valid combinations device family density technology bus width package type temperature range additional ordering options packing type package description s34ml 08g 2 01 bh, tf i, a, v, b 00 0, 3 bga, tsop
document number: 002-00484 rev. *i page 15 of 16 S34ML08G2 11. document history document title: S34ML08G2 8 gb , 4-bit ecc, x8 i/o and 3 v v cc nand flash memory for embedded document number: 002-00484 rev. ecn no. orig. of change submission date description of change ** - xila 04/11/2013 initial release. spansion publication number: S34ML08G2 *a - xila 05/17/2013 performance: reliability - updated addressing: address cycle map table - updated bus cycle data read id: read id for supported configurat ions table - updated 8 gb density for 2nd, 3rd, 4th, and 5th read parameter page: parameter p age description table: correcte d values for bytes 8-9 and 254-255 *b - xila 08/09/2013 read id: read id operation timi ng - 8 gb figure: added values t o i/ox physical interface: updated ts2 48 - 48-lead plastic thin small outline, 12 x 20 mm, package outline figure *c - xila 01/08/2015 performance: package options - a dded 63-ball bga 11 x 9 x 1 mm connection diagram: added figure - 63-bga contact, x8 device, s ingle ce physical interface: added 63- pin ball grid array (bga) ordering information: valid com binations table - added bh to pa ckage type and bga to package description *d 4955117 xila 10/15/2015 updated to cypress template *e 5017336 xila 11/19/2015 fixed formatting issues removed cover page and spansion revision history distinctive characteristics: added industrial plus temperature range ordering information: added a, v, b temperature ranges *f 5160512 xila 04/25/2016 added recommended operat ing conditions section. updated dc characteristics section - updated vcc supply voltag e (erase and program lockout) to "erase and program lockout voltage. updated read param eter page section. updated ordering information section. updated copyright informatio n at the end of the document. *g 5767403 aesatmp8 06/08/2017 upd ated logo and copyright. *h 5893557 mnad 09/26/2017 updated figure 6 . *i 6033716 mnad 01/17/2018 updated sa les page and copyright informa tion.
S34ML08G2 document number: 002-00484 rev. *i revised january 17, 2018 page 16 of 16 ? cypress semiconductor corporation, 2013-2018. this document i s the property of cypress semiconductor corporation and its sub sidiaries, including spansion llc ("cypress"). this document, including any software or firmware included or referenced in th is document ("software"), is owned by cypress under the intelle ctual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and trea ties and does not, except as spec ifically stated in this paragr aph, grant any license under its patents, copyrights, trademark s, or other intellectual property rights. if the software is not accompani ed by a license agreement and you do not otherwise have a writt en agreement with cypress governing the use of the software, th en cypress hereby grants you a personal, non-exclusive, nontransferable li cense (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source cod e form, to modify and reproduce the software solely for use with cypress h ardware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributo rs), solely for use on cypress hardware product units, and (2) under those claims of cypress's patents that are infringed by t he software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware produc ts. any other use, reproduction , modification, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no war ranty of any kind, express or implied, with regard to this docu ment or any software or accompanying hardware, including, but not limited to, the im plied warranties of merchantability and fitness for a particula r purpose. no computing device can be absolutely secure. therefore, despite security me asures implemented in cypress hardware or software products, cy press does not assume any liability arising out of any security breach, such as unauthorized access to or use of a cypress product. in addition, the products described in these materials may contai n design defects or errors known as errata which may cause the product to deviate from published specifications. to the extent permitt ed by applicable law, cypress reserves the right to make change s to this document without further notice. cypress does not ass ume any liability arising out of the application or use of any product or circuit described in this document. any information provide d in this document, including any sample design information or programming code, is provided only for reference purposes. it is the respon sibility of the user of this document to properly design, progr am, and test the functionality and safety of any application ma de of this information and any resulting product. cypress products are not designed, intended, or authorized for use as critical componen ts in systems designed or intended for the operation of weapons , weapons systems, nuclear installations, life-support devices or systems , other medical devices or system s (including resuscitation equ ipment and surgical implants), pollution control or hazardous s ubstances management, or other uses where the failure of the device or sy stem could cause personal injury, death, or property damage ("u nintended uses"). a critical component is any component of a de vice or system whose failure to perform can be reasonably expected t o cause the failure of the device or system, or to affect its s afety or effectiveness. cypress is not liable, in whole or in p art, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all unintended uses of cypress products. you shall in demnify and hold cypress harml ess from and against all claims, costs, damages, and other liabilities, including claims for personal inj ury or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and com binations thereof, wiced, psoc, capsense, ez-usb, f-ram, and tr aveo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete list of cypress trademarks, visit cypress.com. other names and bran ds may be claimed as property of their respective owners. sales, solutions, an d legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution cent ers, manufacturers representativ es, and distributors. to find the office closest to you, visit us at cypress locations . products arm ? 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